synchronous$81107$ - traducción al italiano
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synchronous$81107$ - traducción al italiano

DIGITAL CIRCUIT SYNCHRONIZED BY CLOCK SIGNAL
Synchronous logic; Synchronous system; Synchronous design

synchronous      
adj. contemporaneo, sincrono; simultaneo; sincronistico
Synchronous Dynamic Random Access Memory         
SDRAM FAMILY OF COMPUTER MEMORY TECHNOLOGIES
SDR SDRAM; PC100; Pc100; PC133; Pc133; SGRAM; PC66; Prefetch buffer; Virtual Channel Memory; Prefetch buffer width; VC-RAM; Vcram; SLDRAM; Sldram; SyncDRAM; Syncdram; Synchronous Graphics Random Access Memory; SDRAM; Synchronous Dynamic Random Access; Synchronous dynamic random access memory; PC100 RAM; Synchronous Dynamic Random Access Memory; SDRAM burst ordering; SDRAM burst mode; Synchronous graphics RAM; Synchronous DRAM; Synchronous graphics random-access memory; Synchronous dynamic RAM
Memoria di accesso casuale dinamica sincrona (sincronizzabile secondo l"orologio del computer), SDRAM
synchronous communication         
Synchronous communication; Synchronous transmission
comunicazione sincrona

Definición

synchronous motor
¦ noun an electric motor having a speed exactly proportional to the current frequency.

Wikipedia

Synchronous circuit

In digital electronics, a synchronous circuit is a digital circuit in which the changes in the state of memory elements are synchronized by a clock signal. In a sequential digital logic circuit, data are stored in memory devices called flip-flops or latches. The output of a flip-flop is constant until a pulse is applied to its "clock" input, upon which the input of the flip-flop is latched into its output. In a synchronous logic circuit, an electronic oscillator called the clock generates a string (sequence) of pulses, the "clock signal". This clock signal is applied to every storage element, so in an ideal synchronous circuit, every change in the logical levels of its storage components is simultaneous. Ideally, the input to each storage element has reached its final value before the next clock occurs, so the behaviour of the whole circuit can be predicted exactly. Practically, some delay is required for each logical operation, resulting in a maximum speed limitations at which each synchronous system can run.

To make these circuits work correctly, a great deal of care is needed in the design of the clock distribution networks. Static timing analysis is often used to determine the maximum safe operating speed.

Nearly all digital circuits, and in particular nearly all CPUs, are fully synchronous circuits with a global clock. Exceptions are often compared to fully synchronous circuits. Exceptions include self-synchronous circuits,globally asynchronous locally synchronous circuits, and fully asynchronous circuits.